Semiconductor-based memory, including volatile memory such as dynamic or static random access memory and non-volatile memory such as flash memory have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM), including flash EEPROM, and Electrically Programmable Read Only Memory (EPROM), are among the most popular non-volatile semiconductor memories.
As with most storage devices, semiconductor memory devices may have defective components or storage areas. For example, the individual storage elements or memory cells of a semiconductor memory array may be defective. Additionally, circuitry for the memory array, including word lines, bit lines, decoders, etc., may be defective, rendering associated storage elements defective as well.
Some defect management schemes rely on redundant memory cells to replace primary memory cells that are determined to be defective. During typical semiconductor memory fabrication processes such as that depicted in FIG. 1, wafer level testing 12 is conducted prior to packaging memory chips to form memory devices. A wafer can include hundreds or thousands of memory chips, each of which may include a memory array and peripheral components such as the control and logic circuits for accessing the memory cells of the array. During wafer level testing 12, the functionality of the memory chips is tested so that defective components are not needlessly integrated into a packaged device. Wafer level testing is often conducted at raised and/or lowered temperatures (e.g., 85° C. and/or −30° C.) to ensure functionality at extreme conditions and to ensure functionality after stressing the circuits. Memory cells that fail functionality testing can be replaced with redundant memory cells from the chip. Depending on the type of memory being manufactured, different redundancy schemes can be employed. For example, individual memory cells can be replaced, entire columns or bit lines of memory cells can be replaced, or entire blocks of memory cells can be replaced.
After wafer level testing 12, the wafer is divided into individual memory chips and one or more of the memory chips are packaged 14 to form a memory device. Packaged memory devices are then subjected to a burn-in process 16 to stress the memory arrays and peripheral circuitry of the chips. Burn-in is typically conducted under even higher temperatures (e.g., 125° C.) than wafer level testing. High voltages are applied at various portions of each chip to stress and identify weaker elements. The stress conditions of the burn-in process are designed to cause failure of weaker devices which can later be detected during package level testing 18. In some manufacturing processes, burn-in is not performed.
Package level testing usually consists of various functionality tests to determine which cells are defective subsequent to burn-in. In recent years, techniques such as anti-fuses have been incorporated into fabrication processes so that memory cells that are found to be defective subsequent to burn-in can be replaced by redundant memory from the memory chip.
In some instances, package level testing 18 results in the identification of entire memory chips that are defective. For instance, the number of defective memory cells of the array may exceed the redundancy capacity for the die or certain peripheral circuitry may fail, causing the die to be unusable.
Defective memory die may be rejected 20. However, there problems to overcome when rejecting one memory die in a memory package having multiple memory dice.